New chip design reduces AI energy use

New chip design reduces AI energy use

Cornell researchers create efficient chip architecture to lower energy consumption in AI and other technologies.
GP
Giulio Prisco
Sep 18, 2025
2 min read

A new chip design from Cornell researchers reduces the energy needed to run artificial intelligence (AI) systems, helping make data centers and AI technology more sustainable. As AI grows more powerful, it uses a lot of electricity, raising concerns about its environmental impact. This innovation focuses on making the hardware that powers AI faster and less energy-hungry.

The researchers created a new design for a Field-Programmable Gate Array (FPGA) - a flexible chip that can be reprogrammed for different tasks after it’s made. This makes FPGAs useful for AI, cloud computing, and devices like network cards, medical scanners, and even washing machines. The new design, called Double Duty, makes these chips work better for AI tasks.

How the new design works

Inside an FPGA, there are parts called logic blocks that do the computing work. These blocks have components like Lookup Tables, or LUTs, which handle various logical tasks, and adder chains, which do fast math operations. In older FPGA designs, the adder chains could only work through the LUTs, which slowed things down and wasted energy. The Double Duty design lets LUTs and adder chains work separately at the same time, making the chip more efficient.

This design is especially helpful for deep neural networks. These models are often “unrolled” onto FPGAs, meaning they are turned into fixed circuits for faster processing. The new design makes this process more efficient by using the chip’s strengths. Tests showed that Double Duty permits running the same AI tasks with fewer chips are needed, which saves energy.

The design also helps other fields like wireless communication and chip testing, allowing bigger programs to fit on smaller chips. The work started as an undergraduate project and grew into a major study, involving researchers from Cornell, the University of Toronto, the University of Waterloo, and engineers from Altera. The research was recognized with a Best Paper Award at the 2025 International Conference on Field-Programmable Logic and Applications.

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